module ReadMemory(address, data_in, counter, mem_addr, mem_data, data);
input [31:0] address;
input [1:0] counter;
input [47:0] data_in;
input [15:0] mem_data;
output [31:0] mem_addr;
output reg [47:0] data;

wire is_align;

assign mem_addr = address >> 1;
assign is_align = !address[0];

always @(*) begin
	if(counter == 0) begin
		if(is_align) begin
			data[47:40] <= mem_data[7:0];
			data[39:32] <= mem_data[15:8];
			data[31:0] <= data_in[31:0];
		end else begin
			data[47:40] <= mem_data[15:8];
			data[39:0] <= data_in[39:0];
		end
	end else if(counter == 1) begin
		if(is_align) begin
			data[47:32] <= data_in[47:32];
			data[31:24] <= mem_data[7:0];
			data[23:16] <= mem_data[15:8];
			data[15:0] <= data_in[15:0];
			//data <= {data[47:32], mem_data[7:0], mem_data[15:8], data[15:0]};
		end else begin
			data[47:40] <= data_in[47:40];
			data[39:32] <= mem_data[7:0];
			data[31:24] <= mem_data[15:8];
			data[23:0] <= data_in[23:0];
			//data <= {data[47:40], mem_data[7:0], mem_data[15:8], data[23:0]};
		end
	end else if(counter == 2) begin
		if(is_align) begin
			data[47:16] <= data_in[47:16];
			data[15:8] <= mem_data[7:0];
			data[7:0] <= mem_data[15:8];
			//data <= {data[47:16], mem_data[7:0], mem_data[15:8]};
		end else begin
			data[47:24] <= data_in[47:24];
			data[23:16] <= mem_data[7:0];
			data[15:8] <= mem_data[15:8];
			data[7:0] <= data_in[7:0];
			//data <= {data[47:24], mem_data[7:0], mem_data[15:8], data[7:0]};
		end
	end else begin
		if(is_align) begin
			data[47:0] <= data_in[47:0];
			//data <= {data[47:0]};
		end else begin
			data[47:8] <= data_in[47:8];
			data[7:0] <= mem_data[7:0];
			//data <= {data[47:8], mem_data[7:0]};
		end
	end
end

endmodule